The present invention generally relates to fabricating SONOS type nonvolatile memory devices. In particular, the present invention relates to improved methods of fabricating spacers in SONOS type nonvolatile memory devices.
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), employ a memory cell characterized by a vertical stack of a tunnel oxide, a first polysilicon layer over the tunnel oxide, an ONO (oxide-nitride-oxide) interlevel dielectric over the first polysilicon layer, and a second polysilicon layer over the ONO interlevel dielectric. For example, Guterman et al (IEEE Transactions on Electron Devices, Vol. 26, No. 4, p. 576, 1979) relates to a floating gate nonvolatile memory cell consisting of a floating gate sandwiched between a gate oxide and an interlevel oxide, with a control gate over the interlevel oxide.
Generally speaking, a flash memory cell is programmed by inducing hot electron injection from a portion of the substrate, such as the channel section near the drain region, to the floating gate. Electron injection carries negative charge into the floating gate. The injection mechanism can be induced by grounding the source region and a bulk portion of the substrate and applying a relatively high positive voltage to the control electrode to create an electron attracting field and applying a positive voltage of moderate magnitude to the drain region in order to generate xe2x80x9chot xe2x80x9d (high energy) electrons. After sufficient negative charge accumulates on the floating gate, the negative potential of the floating gate raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel region through a subsequent xe2x80x9creadxe2x80x9d mode. The magnitude of the read current is used to determine whether or not a flash memory cell is programmed. The act of discharging the floating gate of a flash memory cell is called the erase function. The erase function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source region of the transistor (source erase or negative gate erase) or between the floating gate and the substrate (channel erase). A source erase operation is induced by applying a high positive voltage to the source region and a 0 V to the control gate and the substrate while floating the drain of the respective memory cell.
Subsequently, SONOS (Silicon Oxide Nitride Oxide Silicon) type memory devices have been introduced. See Chan et al, IEEE Electron Device Letters, Vol. 8, No. 3, p. 93, 1987. SONOS type flash memory cells are constructed having a charge trapping non-conducting dielectric layer, typically a silicon nitride layer, sandwiched between two silicon dioxide layers (insulating layers). The nonconducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. Since the electrical charge is trapped locally near whichever side that is used as the drain, this structure can be described as a two-transistor cell, or two-bits per cell. If multi-level is used, then four or more bits per cell can be accomplished. Multi-bit cells enable SONOS type memory devices to have the advantage over others in facilitating the continuing trend increasing the amount of information held/processed on an integrated circuit chip.
For simplicity, a two-bit per cell implementation of SONOS is described. While both bits of SONOS type memory devices are programmed in a conventional manner, such as using hot electron programming, each bit is read in a direction opposite that in which it is programmed with a relatively low gate voltage. For example, the right bit is programmed conventionally by applying programming voltages to the gate and the drain while the source is grounded or at a lower voltage. Hot electrons are accelerated sufficiently so that they are injected into a region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it is written, meaning voltages are applied to the gate and the source while the drain is grounded or at a lower voltage. The left bit is similarly programmed and read by swapping the functionality of source and drain terminals. Programming one of the bits leaves the other bit with its information intact and undisturbed.
Reading in the reverse direction is most effective when relatively low gate voltages are used. A benefit of utilizing relatively low gate voltages in combination with reading in the reverse direction is that the potential drop across the portion of the channel beneath the trapped charge region is significantly reduced. A relatively small programming region or charge trapping region is possible due to the lower channel potential drop under the charge trapping region. This permits much faster programming times because the effect of the charge trapped in the localized trapping region is amplified. Programming times are reduced while the delta in threshold voltage between the programmed versus unprogrammed states remains the same as when the device is read in the forward direction.
SONOS type memory devices offer additional advantages as well. In particular, the erase mechanism of the memory cell is greatly enhanced. Both bits of the memory cell can be erased by applying suitable erase voltages to the gate and the drain for the right bit and to the gate and the source for the left bit. Another advantage includes reduced wear out from cycling thus increasing device longevity. An effect of reading in the reverse direction is that a much higher threshold voltage for the same amount of programming is possible. Thus, to achieve a sufficient delta in the threshold voltage between the programmed and unprogrammed states of the memory cell, a much smaller region of trapped charge is required when the cell is read in the reverse direction than when the cell is read in the forward direction.
The erase mechanism is enhanced when the charge trapping region is made as narrow as possible. Programming in the forward direction and reading in the reverse direction permits limiting the width of the charge trapping region to a narrow region near the drain (right bit) or the source. This allows for much more efficient erasing of the memory cell. Although there are advantages associated with SONOS type non-volatile memory devices, there are disadvantages as well. In many instances, it is desirable to form gate transistors in the periphery region with source and drain regions possessing both lightly doped areas and heavily doped areas. This is accomplished by forming spacers adjacent the transistors on the substrate. However, when forming spacers adjacent the memory cells and various gate transistors in the periphery, damage to device often results. This includes damage to the substrate as well as damage to the ONO dielectric layer in the core region. Such damage may cause leakage currents within the device.
For example, referring to prior art FIG. 1, a nonvolatile memory substrate 12 is provided having a core region 14 and a periphery region 16. An ONO dielectric 17 is positioned in the core region 14 over the substrate 12. Flash memory cells 18 are positioned in the core region 14 while gate transistors 20, such as input/out devices, are positioned in the periphery region 16. A spacer material 22 is deposited over the substrate 12. There is extra space 24 between some of the memory cells 18 to subsequently provide for a contact opening.
Referring to prior art FIG. 2, a portion of the spacer material 22 is etched to form spacers 30 adjacent the memory cells 18 and the gate transistors 20. However, in some instances when etching a portion of the spacer material 22, damage 26 to the substrate 12 results and/or damage 28 to the ONO dielectric 17 results. Reliability of the resultant devices is decreased when there is damage 28 to the ONO dielectric 17. And damage 26 to the substrate 12 often creates an undesirable leakage current.
Referring to prior art FIG. 3, a portion of the core region of a memory device is shown with bit lines 32 and word lines 34. The undesirable leakage current 36 (arrow), resulting from the damage 26 to substrate 12 due to etching the spacer material 22 when forming spacers 30, dramatically lowers the operability and reliability of the memory device. There is an unmet need in the art for high quality nonvolatile memory devices.
The present invention provides processes for fabricating SONOS type nonvolatile memory devices. Compared to conventional memory fabrication processes, the present invention provides spacers for transistors in the periphery region while not causing damage to the charge trapping dielectric in the core region or to the substrate in the core region. The present invention also leads to fewer defects, improved reliability, and/or improved scaling.
One aspect of the present invention relates to a method of forming spacers in a SONOS type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.
Another aspect of the present invention relates to a method of forming spacers in a SONOS type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region comprising SONOS type memory cells and the periphery region comprising gate transistors, the SONOS type memory cells comprising a charge trapping dielectric and a poly layer; implanting a first implant into the core region to form buried bit lines in the substrate adjacent the SONOS type memory cells and a first implant into the periphery region to form lightly doped regions in the substrate adjacent the gate transistors; depositing a spacer material over the semiconductor substrate in a substantially conformal manner; masking the core region and forming spacers adjacent the gate transistors in the periphery region by etching a portion of the spacer material over the periphery region; and implanting a second implant into the periphery region to form heavily doped regions in the substrate adjacent the lightly doped regions.